As the integration degree of semiconductor integrated circuit devices (IC) becomes high, transistors as IC constituent elements are made very fine. As a transistor becomes very fine, an operation voltage lowers and the gate insulating film becomes thin. In a system on-chip, there are strong needs for mixing a logical circuit operating at a low voltage with a different circuit such as a flash memory circuit including a flash memory driver circuit operating at a high voltage. In order to realize this, it is necessary to integrate the logical circuit of a low voltage operation and the flash memory driver circuit of a high voltage operation on the same semiconductor substrate.
In configuring a CMOS circuit, n-channel transistors operating at high and low voltages and p-channel transistors operating at high and low voltages are formed.
FIGS. 11A to 11F illustrate a typical manufacture method for such a semiconductor device.
As shown in FIG. 11A, a shallow isolation trench (shallow trench isolation: STI) 102 buried with an insulating film is formed in a silicon substrate 101 by well-known processes. In FIG. 11A, four active regions defined by STI are shown. In two active regions on the left side in FIG. 11A, two n-channel MOS transistors N-LV and N-HV are formed having a thin gate insulating film for low voltage (LV) and a thick gate insulating film for high voltage (HV), respectively.
In two active regions on the right side in FIG. 11A, two p-channel MOS transistors P-LV and P-HV are formed having a thin gate insulating film for low voltage (LV) and a thick gate insulating film for high voltage (HV), respectively.
First, a photoresist mask PR51 having an opening corresponding to an n-channel MOS transistor region is formed to perform p-type impurity ion implantation for forming p-type wells WP, p-type impurity ion implantation for forming channel stop regions CSP under the isolation region for isolating semiconductor elements formed in active regions, and p-type ion impurity implantation Vt1 for setting a threshold voltage Vt of the transistor having the thick insulating film to a desired value. The photoresist mask PR51 is thereafter removed.
As shown in FIG. 11B, a photoresist mask PR52 having an opening corresponding to a p-channel MOS transistor region is formed to perform n-type impurity ion implantation for forming n-type wells WN in the p-channel MOS transistor region, n-type impurity ion implantation for forming channel stop regions CSN under the isolation region, and n-type ion impurity implantation Vt2 for setting a threshold voltage Vt of the p-channel MOS transistor having the thick insulating film to a desired value. The photoresist mask PR52 is thereafter removed.
In the above-described ion implantation processes, the threshold voltage control is performed for the transistor regions N-HV and P-HV having the thick gate insulating films. The ion implantation is insufficient for the threshold voltage control in the transistor regions N-LV and P-LV having the thin gate insulating films.
As shown in FIG. 11C, a photoresist mask PR53 having an opening corresponding to the n-channel MOS transistor region N-LV having the thin gate insulating film is formed to perform additional p-type impurity ion implantation Vt3 for adjusting the threshold voltage of the n-channel MOS transistor region N-LV having the thin gate insulating film. The photoresist mask PR53 is thereafter removed.
As shown in FIG. 11D, a photoresist mask PR54 having an opening corresponding to the p-channel MOS transistor region P-LV having the thin gate insulating film is formed to perform additional n-type impurity ion implantation Vt4 for adjusting the threshold voltage of the p-channel MOS transistor region P-LV having the thin gate insulating film. The photoresist mask PR54 is thereafter removed. Next, a thick gate insulating film GI1 is formed on the whole surface of the semiconductor substrate.
As shown in FIG. 11E, a photoresist mask PR55 is formed on the grown gate insulating film, covering the transistor region having the thick gate insulating film and exposing the transistor region having the thin gate insulating film. By using the photoresist mask PR55 as an etching mask, the gate insulating film GI1 is removed. The photoresist mask PR55 is thereafter removed.
As a thin gate insulating film is formed on the semiconductor substrate, a thin gate insulating film GI2 is formed in the region where the thick gate insulating film is removed. In this manner, the thick gate insulating film GI1 and thin gate insulating film GI2 are formed.
As shown in FIG. 11F, a gate electrode layer of polysilicon is formed on the gate insulating film and patterned to form gate electrodes G. By using the gate electrodes as a mask, ion implantation is performed for the extension regions of source/drain regions. After side wall spacers of silicon oxide or the like are formed, ion implantation is performed to form high impurity concentration source/drain regions. Ion implantation processes for the n- and p-channel MOS transistors are selectively executed by using resist masks.
In this manner, a CMOS semiconductor device is formed as shown in FIG. 11F. According to the above-described manufacture method, four masks are used and eight ion implantation processes are executed for forming wells and controlling the threshold voltage Vt excepting the formation of gate insulating films. Complicated manufacture processes result in an increase in manufacture cost and a reduction in manufacture yield. It is desired to simplify the manufacture processes.
Japanese Patent Laid-open Publication No. HEI-11-40004 proposes a semiconductor manufacture method with a reduced number of processes. The semiconductor manufacture method with a reduced number of processes will be described below.
As shown in FIG. 12A, similar to FIG. 11A, four active regions N-LV, N-HV, P-LV and P-HV are defined in a silicon substrate 101 by an isolation region 102. A photoresist mask PR51 having an opening corresponding to an n-channel transistor region is formed, and ion implantation is performed three times to the n-channel MOS transistor region to form p-type wells WP, p-type channel stop regions CSP and p-type threshold voltage adjusting regions VtP.
A concentration of ions to be implanted for adjusting the threshold voltage is set to a value suitable for the transistor N-LV having a thin gate insulating film. This concentration is too high for the impurity ion implantation for adjusting the threshold voltage of an n-channel MOS transistor N-HV having a thick gate insulating film. The photoresist mask PR51 is thereafter removed.
As shown in FIG. 12B, a photoresist mask PR52 having an opening corresponding to a p-channel MOS transistor region is formed, n-type impurity ions are implanted to form n-type wells WN, n-type channel stop regions CSN and n-type threshold voltage adjusting regions VtN, in the p-channel MOS transistor region.
A concentration of ions to be implanted for adjusting the threshold voltage is set to a value suitable for the p-channel MOS transistor P-HV having a thick gate insulating film. This concentration is insufficient for a p-channel MOS transistor P-LV having a thin gate insulating film. The photoresist mask PR52 is thereafter removed.
As shown in FIG. 12C, a photoresist mask PR56 is formed having an opening corresponding to the n-channel MOS transistor region N-HV having the thick gate insulating film and the p-channel MOS transistor region P-LV having the thin gate insulating film, and n-type impurity ions are additionally implanted. With two n-type impurity ion implantation processes, the p-channel MOS transistor region P-LV having the thin gate insulating film has a desired impurity concentration and its threshold voltage is adjusted properly.
In the n-channel MOS transistor region N-HV having the thick gate insulating film, too high the p-type impurity concentration by the first ion implantation is compensated by the additional n-type impurity ion implantation and the impurity concentration lowers. The photoresist mask PR56 is thereafter removed.
As shown in FIG. 12D, a thick gate insulating film GI1 is formed. By using as an etching mask a photoresist mask PR55 covering the transistors having the thick gate insulating film, the thick gate insulating film is removed from the region where a thin gate insulating film is to be formed. The photoresist mask PR55 is thereafter removed, and a thin gate insulating film GI2 is formed.
As shown in FIG. 12E, gate electrodes, source/drain regions and the like are formed by well-known processes to complete a semiconductor device.
With this method, the impurity concentration distributions in the wells are formed by three masking process and seven ion implantation processes, excepting the selective removal of the gate insulating film. As compared with the processes show in FIGS. 11A to 11D, one mask is reduced and one ion implantation process is reduced.
Although the manufacture processes are simplified, the threshold voltage Vt of the n-channel MOS transistor N-HV having the thick gate insulating film is not set independently. Compromise to some degree is necessary for setting the threshold voltage Vt. If a threshold voltage setting is changed at a design stage, threshold voltage settings for other transistors are required to be changed in some cases.
In manufacturing a plurality kind of transistors operating at a number of different operation voltages, the number of processes is likely to increase. New problems are likely to occur if the manufacture method with a reduced number of processes is adopted. A semiconductor device operating at a plurality of operation voltages is desired which can be manufactured by a simplified manufacture method.